Traps And interrupts

Traps and interrupts are events that break down the normal execution of the program.

Trap: A trap is and abnormal condition detected by the CPU, which indicates an unknown I/O device is accessed, etc.

Interrupt: An interrupt in an interruption in the normal execution of the program. When the CPU is interrupt, then it stops its current activities like execution of the program. And transfer the control to interrupting device to check the interrupt. The CPU responds interrupt. By saving the current value of the program counter and resetting the program to a new address. The new address is the starting address where procedure for handling interrupt is located. Similarly, other state information is also saved when an interrupt occurs. In many computer systems this information is stored in a special program status word register. After saving the necessary information, the interrupt service routine is executed on completion; the CPU resumes the interrupted program. Thus the application program does not have to contain any special code to accommodate the interrupts. The CPU and the operating system are responsible for suspending the program and then resuming it at the end of interrupt processing.

Difference:

1. A trap will occur at exactly the same point f the program execution, each time a program runs.

2. An interrupt is dependent on the relative timing between the interrupting device and the CPU.

An interrupt is signal sent to the CPU by an external hardware device such as I/O device. The software can also send interrupt signal to the CPU. Hardware may trigger an interrupt at any time sending a signal to the CPU through system bus. It also called a monitor call or supervisor call.

Interrupt are the important part of computer architecture. Each machine has its own interrupt mechanism, bur most of the function are common. The interrupt must transfer control to the appropriate interrupt service routine. Similarly, interrupts must be handled quickly. In a computer system only a predefined interrupts can be occurred, so the array of pointer is used to store the address of interrupt routines. This array of pointer is called the interrupt vector. Each trap and interrupt is associated with an index into that vector. The index values are the unique device number that provides the address of the interrupt service routine for interrupting device. The early computer systems stored the interrupt address in a fixed location or in a location indexed by the device number but the modern computer use the stack for this purpose.

Classes of interrupts:

There are many classes of interrupts, but the most common classes of interrupts are

·                    Program check interrupts

·                    Supervisor call interrupts

·                    Timer interrupts

·                    I/O interrupts

·                    External interrupts

·                    Machine check interrupts

Program check interrupts:

These are caused by some problems that may occur during program execution such as division by zero, arithmetic overflow or underflow, data read in correct format, attempt to reference a memory location beyond the limits of real memory, attempt to reference a protected resource etc. many systems allow users to specify their own routines to be executed when a program check interrupt occurs.

Supervisor call interrupts:

These are initiated by a running process that executes the supervisor call instruction. This type of interrupt is a user generated request for a particular system service such as for I/O operation etc.

Timer interrupts:

These are generated by timer within the CPU. Timer interrupt allows the operating system to perform certain function on regular intervals of time.

I/O interrupts:

These are generated by I/O controller. The i/o interrupts signal to the cpu that the status of device has changed. I/O interrupts are caused due to three resigns.

1. Input/output operation completes.

2. Input/output error occurs.
3. Input/output device is made ready.

External interrupts:

These are caused by pressing of the console’s interrupt key by the operation or the receipt of a signal from another processor on a multiprocessor system.

Machine check interrupts:

These are caused by hardware failure such as memory parity error.